EDN

Static crosstalk analysis assures silicon success

With the rapid move to ultradeep submicron designs and feature size processes of 0.13 micron and below, ensuring the integrity of signals as they traverse conductors on a chip is becoming a challenge.
EDN

Is static timing analysis still valid?

SAN MATEO, Calif. — Static timing analysis is one of the pilings upon which the whole edifice of modern IC design has been erected. But this vital technique itself rests upon assumptions that may no ...
Design-Reuse

Optimizing Floorplan for STA and Timing improvement in VLSI Design Flow

Static timing analysis is a technique of computing of cell delay and interconnect delay in design (known as path delay) and comparing it against constrain (timing specific) set in SDC file. This paper ...
Semiconductor Engineering

Rapid Timing Constraints Signoff With Automated Constraint Management

Signoff of a system on chip (SoC) or IP design has multiple aspects, but often timing closure is the most challenging. Early use of a static timing analysis (STA) tool is clearly important, and such a ...
Electronic Design

Oh, The Pain (Of Timing Closure At 28 nm)

What to do, what to do? Chip complexity continues to grow and design schedules are more aggressive, yet design teams are staying the same size or even being scaled back. Something has to give. A key ...